Question
Let’s design a low power and minimum area smartwatch. Please optimize the NMOS transistor PPA (Power, Performance, Area) in the table. Optimization plans should be clear and concise. You may add >2 plans. To simplify, fclk=1MHz for all plans.
Please check the transistor model carefully. This model is the source of all values.
dP(%)= Power difference
dA(%)= Area difference
Submission: Please upload a single doc here and add hand calculations.
| PPA Target | Total Points =100 | Plan | Vth (V) | Ion (mA) | Operating Region | Ctot (pF) | Average Dynamic Power (mW)= CtotV2fclk | dP(%) | Area (um2) | dA(%) | Target Achieved? If Not, explain why in 1-2 sentences. |
| Initial Reference | 10 | Plan1: VGS=2V, VDS=1V, W/L=1 | |||||||||
| <50% Power reduction only | 30 | Plan1=? | |||||||||
| Plan2=? | |||||||||||
| <50% Area reduction only | 30 | Plan1=? | |||||||||
| Plan2=? | |||||||||||
| <50% both Power and Area reductions | 30 | Plan1=? | |||||||||
| Plan2=? |
* Transistor models
* Level=3 models
*
.MODEL N_1u NMOS LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5
+ PHI = 0.7 VTO = 0.8 DELTA = 3.0
+ UO = 650 ETA = 3.0E-6 THETA = 0.1
+ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3
+ RSH = 0 NFS = 1E12 TPG = 1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5
*
.MODEL P_1u PMOS LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6
+ PHI = 0.7 VTO = -0.9 DELTA = 0.1
+ UO = 250 ETA = 0 THETA = 0.1
+ KP = 40E-6 VMAX = 5E4 KAPPA = 1
+ RSH = 0 NFS = 1E12 TPG = -1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5
*
*
| Hand Calculations | |
| Initial Reference | |
| <50% Power reduction only Plan1Plan2 | |
| <50% Area reduction only Plan1Plan2 | |
| <50% both Power and Area reductions Plan1Plan2 |
